A 400-MHz Processor for the Conversion of Rectangular to Polar Coordinates in 0.25- m CMOS

This paper describes the architecture and IC implementation of a rectangular-to-polar coordinate converter for digital communication applications. The architecture core uses small lookup ROMs, fast multipliers, and a single angle-rotation stage. Area and latency are reduced in comparison with traditional methods. The processor, implemented in 0.25m five-metal CMOS, has 14-b in-phase and quadrature channel inputs and 15-b magnitude and phase channel outputs. The phase and magnitude calculations have a maximum error of 0.00024 (0.0078% of ) and 0.03 (1% of 2 2), respectively. Computational latency is 19 cycles, and power dissipation is 470 mW at 2.5 V and 406 MHz (Mconversions/s).